The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for remotely testing an integrated circuit chip or other microelectronic device over the Internet.
Very large integrated circuit chips such as Programmable Logic Devices (PLD) and Application Specific Integrated Circuits (ASIC) are extremely intricate devices that are fabricated using a large number of precise and critical processing steps. Unfortunately, technology has not advanced to the point at which such a device can be fabricated with perfect reliability and be expected to never fail.
There are many ways in which a device can partially or completely malfunction, and it can be difficult to diagnose the source of a particular failure mode. The problem is exacerbated by the fact that integrated circuits are not used by themselves, but are components that are plugged into sockets on circuit boards that also include a number of other interconnected components. A particular malfunction can be the result of not only an internal fault in a chip, but from other components on the board and/or the manner and functionality in which the components are interconnected.
Programmable integrated circuit devices such as PLDs are fabricated and subjected to extensive testing at a manufacturing facility, and then shipped to customers who program the devices to implement their own required functionality. The programmed devices are assembled onto boards as described above and connected to power supplies and additional components to produce finished electronic products. The boards often include nonvolatile memories that program the PLDs ever time power is turned on. These products are then tested and shipped to consumers.
A PLD or other device can fail immediately or after a period of use. The testing procedure for a finished product occurs both at the time of its initial manufacture and when it is returned to the manufacturer for repair.
In order to facilitate testing of large integrated circuits such as PLDs, a methodology has been formulated by the Joint Test Action Group (JTAG) and codified as IEEE specification no. 1149.1. The methodology includes adding special microelectronic components known as xe2x80x9cboundary scan circuitryxe2x80x9d to the integrated circuit chips. This circuitry enables test signals known as xe2x80x9cvectorsxe2x80x9d to be applied to the input pins of the chip and resulting output signals to be read at the output pins. Although the testing can be performed without removing a chip from its socket, the testing is isolated to the internal functionality of the chip and is unaffected by the other components on the board.
Depending on the manner in which the individual elements of the chip are fabricated or programmed to perform a particular function, a set of test vectors is generated such that every testable logic element in the chip will be subjected to a test that determines if the individual element is functioning properly. For every input vector there will be a resulting output signal that will have a particular value if there is no malfunction. If the actual output signals match the expected values, the testing will indicate that there are no damaged or malfunctioning elements in the chip.
Although boundary scan circuitry is provided in a large number of integrated circuit chips being currently fabricated, many customers do not have the ability to perform the tests and/or generate a suitable set of test vectors. If there is a malfunction, they return the chip to the manufacturer with an indication that it did not function properly. Often a customer will ask the manufacturer to test the chip and/or troubleshoot the problem.
Manufacturers generally have a procedure known as xe2x80x9creturn material authorization (RMA)xe2x80x9d by which the customer calls the manufacturer to obtain an RMA number and returns the chip by mail with the RMA number marked on the outside of the package. Preferably, the customer will inform the manufacturer either at the time of the call or by means of a letter in the package as to the nature of the problem.
When the manufacturer receives the allegedly defective chip, the chip will be sent to a failure analysis (FA) group which performs a series of tests on the chip to determine if it is in fact defective. If the customer provided device data in the form of device specific program code indicating the functionality that was programmed into the chip, the FA group can generate a set of test vectors specific to the chip and perform boundary scan testing. The FA group can make internal tests as well. This testing can also be performed using a generic set of test vectors.
Other tests include physical examination of the chip, typically using a microscope, to locate damaged pins, etc. The protective cap can also be removed and the semiconductor die itself can be examined under a microscope.
Assuming that the chip itself is defective, the FA group will hopefully isolate the cause of the defect and thereby produce a solution to the problem. However, it is often the case that the chip is not defective, but is programmed improperly and/or integrated with the other components on the circuit board to cause logical, signal or timing errors. A solution to a problem of this type cannot be found by testing the chip itself.
The RMA/FA procedure as presently being practiced is subject to several serious drawbacks. First, the chip must be physically removed from the apparatus in which it is incorporated and shipped to the manufacturer. This takes an undesirably long time during which the apparatus is unavailable and inaccessible for further troubleshooting. In addition, removal of the chip can result in damage to the pins.
The FA procedure is also lengthy and labor intensive. This means that the customer must wait an extended period of time for a solution to his problem, which is especially undesirable either if the apparatus is in the process of development or if the board is left inoperable.
Further, the FA analysis may not produce an answer to the problem if the error was in another component that was connected to the chip. For these reasons, a need exists in the art for a method of quickly testing a customer""s integrated circuit chip in his own facility and in the environment in which it is functionally connected.
The present invention overcomes the drawbacks of the prior art and provides a method that enables an integrated circuit chip to be quickly tested remotely and in situ.
More specifically, the present invention uses the Internet or other electronic communication media to test an integrated circuit chip that is provided with boundary scan or other suitable circuitry and plugged into a circuit board at a customer""s facility.
A host computer at the manufacturer""s facility runs a web page server including the ability to remotely test a customer""s chip. The process is initiated by the customer connecting the circuit board to his own computer and logging onto the web site. The customer transmits identification and other data to the web server, which then transmits a downloader program and a JAVA program script to the customer""s computer. Alternatively, the downloader program can be previously supplied to the customer and used to log onto the web site.
The customer""s computer then uses the downloader program to transmit high and low level device data describing the functionality of the chip to the host computer, which then generates and transmits a set of suitable test vectors to the customer""s computer. Then, the customer""s computer tests the chip using the boundary scan circuitry and test vectors and transmits the test results to the host computer, which then produces and transmits an evaluation of the results to the customer""s computer.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.